Figure 12 from Air spacer for 10nm FinFET CMOS and beyond

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From FinFET to Nanosheets and Beyond

Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era - ScienceDirect

Figure 4 from FinFET With Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits

a) 3D view of the bulk FinFET tri-gate structure, b) 3D cross section

Figure 8 from Air spacer for 10nm FinFET CMOS and beyond

IEDM 2022 – TSMC 3nm - SemiWiki

Impact of MOL/BEOL Air-Spacer on Parasitic Capacitance and Circuit Performance at 3 nm Node

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